In general, EEPROM cells have floating gates similar to erasable programmable read only memory (EPROM) cells. Further, EEPROM cells and EPROM cells are programmed or erased by injecting electrons into the floating gates or ejecting the electrons out of the floating gates. However, mechanisms for injecting electrons and ejecting electrons of EEPROM cells are quite different from those of EPROM cells.
In an EPROM cell, channel hot electrons, which are accelerated from a source region toward a drain region, are injected into the floating gate during the programming operation, and the electrons stored in the floating gate are ejected by energy of ultra-violet (UV) light during the erasing operation. However, in an EEPROM cell, the programming operation and erasing operation are achieved by Fowler-Nordheim (FN) tunneling current that flows through a tunnel oxide layer under a high electric field of about 10 MV/cm.
Typically, a floating gate tunnel oxide (FLOTOX) based-type memory of EEPROM device has a unit cell composed of two transistors, e.g., a selection transistor for addressing a desired cell and a memory transistor for storing data. The memory transistor includes a floating gate where the data is stored, a control gate electrode for controlling the operation of the memory transistor, and an inter-gate dielectric layer interposed between the floating gate and the control gate electrode.
FIGS. 1 to 3 are cross sectional views illustrating a conventional method of fabricating an EEPROM cell.
Referring to FIG. 1, a first photoresist pattern 14 is formed on a semiconductor substrate 10. The photoresist pattern 14 is formed having an opening that exposes a predetermined region of the semiconductor substrate 10. Impurity ions are implanted into the semiconductor substrate 10 using the photoresist pattern 14 as an implantation mask, thereby forming a buried N+ region 16.
Referring to FIG. 2, the photoresist pattern 14 is removed, and a gate oxide layer 12 is formed on the semiconductor substrate where the photoresist pattern 14 is removed. A second photoresist pattern 15 is formed on the gate oxide layer 12. The second photoresist pattern 15 has an opening that exposes the gate oxide layer 12 on the buried N+ region 16. The gate oxide layer 12 is etched using the second photoresist pattern 15 as an etching mask, thereby exposing the buried N+ region 16 and defining a tunnel region 20 on the buried N+ region 16.
Referring to FIG. 3, the second photoresist pattern 15 is removed, and a tunnel oxide layer 22 is formed in the tunnel region 20. Subsequently, a memory gate 34 and a selection gate 36, which are spaced apart from each other, are formed on the substrate having the tunnel oxide layer 22. The memory gate 34 is formed having a floating gate 24a, an inter-gate dielectric layer 30a and a control gate electrode oxide layer, which are sequentially stacked over the tunnel region 20. The selection gate 36 is formed having a lower selection gate 24b, an inter-gate dielectric layer 30b and an upper selection gate 32b, which are sequentially stacked on the gate oxide layer 12. Though not shown in the figure, the lower selection gate 24b is electrically connected to the upper selection gate 32b. Impurity ions are then implanted into the semiconductor substrate 10 using the memory gate 34 and the selection gate 36 as implantation masks, thereby forming a cell depletion region 38 and source/drain regions 40 and 42.
According to the foregoing method, the buried N+ region 16 and the tunnel region 20 are defined by two separate and different photolithography steps. Accordingly, the tunnel region 20 may be misaligned with the buried N+ region 16 as shown in FIG. 4.
FIG. 4 is a cross sectional view illustrating a pair of FLOTOX-based EEPROM cells, which are formed to be symmetrical about a common source region 40 shared by a pair of EEPROM cells. Each of the pair of EEPROM cells has the same structure as shown in FIG. 3.
Referring to FIG. 4, the tunnel regions 20 may be shifted toward a single direction by a distance “a” due to the misalignment that occurs during the photolithography process for defining the tunnel regions 20. As the distance “a” increases, the overlap area between the tunnel oxide layer 22 and the buried N+ region 16 can be reduced, thereby significantly decreasing the program and erasure efficiency of EEPROM cells.
Therefore, there is a need for EEPROM cells having uniform overlap areas between the tunnel regions and the buried N+ regions throughout the substrate to improve program, erasure and read operations of EEPROM devices.